Intel Offers Free Webinar Series

Intel Webinar

Intel Offers Free Webinar Series

Intel is pleased to announce their free fall series of webinars that are targeted at software developers who are targeting high-performance compute for the technical and enterprise segment. 

The series runs from September through November 2013, and encompasses the announcements of our latest tools, plus instructional tips and techniques on parallelization, vectorization, distributed computing, and analysis with Intel® Software Development tools targeting Intel® Xeon™ Processors and Intel® Xeon Phi™ Coprocessors.

Sharpen your development skills with the expert technical teams at Intel, and hear open source innovators discuss development tools, programming models, vectorization and execution models that will get your development efforts powered up to get the best out of your applications and platforms.



Times indicated are Pacific time . . .


Oct 15 9:00 A.M. PDT
Powered by MKL Accelerating NumPy and SciPy Performance with Intel® MKL- Python

NumPy/SciPy are scientific libraries for Python. R is a programming language for statistics computing. These tools, especially their open source packages, have gained popularity among programmers in scientific and statistic computing. A fundamental component in both NumPy/SciPy and R are the linear algebra functions, which rely on the standard BLAS and LAPACK routines. Intel® Math Kernel Library (Intel® MKL) provides a high performance implementation of BLAS and LAPACK that is optimized for Intel architectures. This webinar discusses building the open source NumPy/SciPy and R with Intel MKL to significantly improve the performance of linear algebra operations. Beyond BLAS and LAPACK, there are other functions in Intel MKL that can provide great performance benefit. This webinar will give a quick tutorial on how to extend NumPy/SciPy and R by writing a wrapper for an Intel MKL function and then use it from NumPy/SciPy or R programs.
Presenter:  Zhang Zhang / Vipin Kumar


Oct 22 9:00 A.M. PDT
Introduction to OpenMP 4.0 for SIMD and Affinity Features with Intel® Xeon Processors and Intel® Xeon Phi™ Coprocessors

Continuing its long tradition of standards-based software products, Intel® has implemented new OpenMP features that enhance the usage of its hardware products.  The newly-released OpenMP 4.0 specification ( contains several features that are especially useful with Intel® Xeon Phi™ coprocessors.  The accelerator feature is a standardized way to program off-loading computations to such devices.  The SIMD feature is a standardized way to engage the 512-bit wide SIMD capability on Intel® Xeon Phi™ coprocessors.  The affinity feature gives users the ability to pin threads to cores in a new, more sophisticated way.  Taken together, these OpenMP 4.0 features can help the user maximize performance on the new Intel® Xeon Phi™ coprocessors, while at the same time always applying to standard Intel® Xeon processors, preserving your software investment.
Presenter:  Michael Klemm


Oct 29 9:00 A.M. PDT
Secrets of Performance Profiling – An Introduction to Intel® VTune™ Amplifier XE

Intel® VTune Amplifier XE is a powerful performance profiler with many highly-configurable ways to collect and view data. This webinar will introduce the most common and efficient ways for new users to identify performance issues in their applications. It will describe the key concepts of performance analysis including the Best-Known-Methods for identifying the low hanging fruit in the performance tuning process.
Presenter: Gary Carelton


Oct 29 11:00 A.M. PDT
Profiling MPI Communications – Tips and Techniques for High Performance

Is your MPI application performing optimally on your cluster? Understanding MPI application behavior, quickly finding bottlenecks, and achieving high performance for parallel cluster applications is critical. Join us as we show how to effectively analyze MPI performance, speed up parallel application runs, locate hotspots and bottlenecks, and compare trace files with graphics providing extensively detailed analysis and aligned timelines.
Presenter:  Gergana Slavova / James Tullos


Oct 30 9:00 A.M. PDT
Advanced Profiling with Intel® VTune™ Amplifier XE Part 1: Find the bottleneck

Learn how to use Intel(r) VTune(tm) Amplifier XE to find the primary microarchitectural bottleneck in your application. See an in-depth demo of the “General Exploration” analysis type, and a case study on interpreting General Analysis results and making iterative optimizations.
Presenter:  Jackson Marusarz


Oct 30 11:00 A.M. PDT
Advanced Profiling with Intel® VTune™ Amplifier XE Part 2: Tune for Haswell (Sandy Bridge and Ivy Bridge)

Build on the knowledge from part 1. Learn to identify the common sources of microarchitectural bottlenecks in modern software. For each issue, you’ll learn why it matters, what causes it, some techniques to resolve it, and where to find follow-up resources.
Presenter:  Shannon Cepeda


Nov 5 9:00 A.M. PST
Software Architects: Design and Prototype Scalable Threading using Intel® Advisor XE

Breakthrough techniques for threading design let architects and lead designers quickly evaluate alternative designs. Project threading performance impact for systems with from 2 to 512 cores. Learn how to quickly compare the performance scaling of alternative threading designs and find synchronization errors before investing in implementation. Evaluate alternative designs without disrupting normal development.
Presenter:  Ravi Kumar Vemuri


Nov 6 9:00 A.M. PST
Precision Memory Leak Detection Using the New On-Demand Leak Detection in Intel® Inspector XE

Intel Inspector XE now gives you the ability to set and reset memory baselines and ask for memory leak information from your program whenever you want it. You will learn how to skip analysis of sections of the code you are not interested in, how to choose whether memory growth or on-demand leak detection is the right tool for you, and how to choose the correct analysis level to use, whether you are looking for that one pesky leak or looking to set up a QA process to find future leaks.
Presenter:  Hollly Wilper


Nov 12 9:00 A.M. PST
Porting and Tuning of Lattice QCD* and MPI-HMMER* for Intel® Xeon Processors & Intel® Xeon Phi™ Coprocessors

The Intel Xeon Phi architecture from Intel Corporation features parallelism at the level of many x86-based cores, multiple threads per core, and vector processing units. Lattice Quantum Chromodynamics (LQCD) is of importance in studies of nuclear and high energy physics and MPI-HMMER is an open source MPI implementation of the HMMR protein analysis suite and important to life science research. Technical experts at Intel describe the process and experience with optimizing key kernels for the Intel® Xeon Phi™ coprocessor and to achieve performance on the applications with the addition of an Intel® Xeon Phi™ coprocessor over a Intel® Xeon E5 system.
Presenter:  Frances Roth